Semiconductor manufacturers face a constant challenge to comply with Moore's Law. They constantly strive to continually decrease feature sizes, such as active and passive devices, interconnecting wire widths and thicknesses and power consumption as well as to increase device density, wire density and operating frequencies.
Generally, a buried channel disposed in a metal oxide semiconductor (MOS) device is developed to overcome a problem of random telegraph signal (RTS). However, a higher concentration and a deeper depth of the buried channel may lead to problems such as current leakage and an uncontrollable threshold voltage. To overcome the problems, the circuit of a logic area in the device needs to be modified to match a new design of the buried channel.
Therefore, there is a need to develop a semiconductor device and a method of fabricating the semiconductor device to tackle the aforementioned problems without greatly changing the original circuit design of the device.